The invention relates to graphics display by electronic devices. More particularly, the invention relates to stretch blitting operations of graphics that are displayed by electronic devices.
Personal computers have been working their way into daily household use for over two decades. Games for education and entertainment, already have strong applications for the PC and are enhanced by the introduction of 3D graphics. Real-time photo-specific textured 3D graphics will provide accurate simulations of real world locations, viewable with full viewpoint freedom.
The key to high quality real-time 3D graphics is to have a system architecture and memory access scheme that supports the rendering of cluttered scenes where there are several layers of objects driving up the number of pixel memory accesses. The associated processing loads must not reduce system update rate below what we consider real-time (30 Hz). Some proposed solutions off-load processing onto the application""s shoulders and thus have trouble rendering simple scenes in real-time. Better accelerators will accelerate those hardware functions that are processor-intensive, leaving the processor free for high-level functions. Generally, custom acceleration hardware (ASICxe2x80x94silicon) executes rendering functions much faster, leaving more time for the software application. This graphics 3D rendering engine, or 3D pipeline, uses a significant number of multiplication and addition circuits.
Video conferencing and other video image manipulation is also coming to the desktop. One desirable feature to be used in a video teleconference is the ability to scale a video image to various sizes prior to transmission. Smaller images, while providing less detail, require less communication bandwidth and can be reproduced by a recipient computer more quickly. Generally, a camera will generate a video image having a maximum size defined by the camera""s image sensor. The image can then be scaled to a smaller or larger image by a scaling apparatus.
Existing video cameras that employ digital filtering of source pixels to provide a scaled output are designed to produce each output pixel in a single cycle of the source pixel clock. In other words, each of the taps of a multi-tap filter must be applied in the same clock cycle. Consequently, a significant number of multiplication and addition circuits are required to process each separate filter tap in parallel. As the number of multiplication and addition circuits increases, filter propagation delay and power consumption also increase. Further, where the scaling apparatus is implemented in an integrated circuit (IC), the increased number of multiplication and addition circuits translates to an increased die size of the implementing IC. The net result is a more expensive scaling engine.
As computer systems include 3D rendering as well as video imaging systems, the hardware assist for speeding up calculations is becoming expensive in terms of area as well as gates. Therefore, it would be advantageous if the number of gates for an imaging system including three-dimensional rendering and video scaling would be reduced.
A method and apparatus for image scaling is provided. A 3D pipeline comprises a command stream controller to enable a rectangle mode. The 3D pipeline including a windower to produce addresses for the rectangle defined by the vertices. A filter interpolates between neighboring points, based on relative location, to generate attributes for each pixel. A color calculator aligns output data and writes the output data to a destination surface.